The Spartan 6 FPGA Family offers leading system integration abilities at the lowest total cost when it comes to high-volume applications. The different series within the Spartan 6 family offer a host of densities ranging between 3,840 and over 147,000 logic cells. The systems consume half the power previous systems used and are much faster and more comprehensive when it comes to connectivity.
Cost Effective And Ideal Balance Of Performance
Built on advanced low-power, 45-nm copper-process innovation which provides an ideal balance of performance, power, and cost. The systems offer proprietary and more efficient 6-input, dual-register LUT or look-up table logic and diverse in-built system block selections. They include 2×9 Kb (18Kb) block RAMs; SDRAM memory controllers; second-generation DSP48A1 slices; high-speed power-optimized serial transceiver blocks; improved clock-management blocks; advanced power controlling modes; Express PCI compatible Endpoint blocks; enhanced Internet Protocol security with DNA protection and AES; and auto-detect configurations selections.
All of these features offer a cost-effective, yet programmable, alternative to bespoke ASIC products that deliver unsurpassed ease of use. The Spartan 6 FPGA family offers the best solutions when it comes to creating cost-effective embedded applications, consumer-focused DSP designs, and high-volume logic designs. These systems create the programmable silicon foundation required by Targeted Design Platforms aimed at delivering integrated hardware and software components that designers need to focus on innovation once the development cycle commences.
Spartan 6 FPGA Family Features
The Spartan 6 FPGA family consists of two main series, the Spartan 6 LX FPGA series, which is a optimized logic system, and the Spartan 6 LXT FPGA series, which is a serial connectivity high-speed system. These systems are designed to be cost-effective. This is achieved through integrating multiple integrated blocks, high volume wire-bonded plastic packages, staggered pads, and an optimized assortment of I/O standards.
The systems use dynamic and low static power. Their 45nm process is optimized for low power and cost. This means that their hibernate power down mode consumes zero power, while suspended mode maintains configuration and state through a multi-pin wake up and control enhancement. The systems also feature multi-standard, multi-voltage Select IO interface banks which allow for +1,000 Mb/s data transfer rates per I/O. They also feature hot-swap compliance, low-cost SSTL and HSTL memory interfaces, 1.2V to 3.3V I/O protocols and standards, and flexible I/O slew rates for improved signal integrity.
Another notable feature of Spartan 6 high performance fpga family systems is its incorporated Endpoint PCI Express designs block. They boast low-cost PCI technology support that is compatible with 33MHz 64bit and 32bit specifications. Their powerful DSP48A1 slices ensure high-performance signal and arithmetic processing, and feature cascading and pipelining capabilities. At the same time, they have a 48bit accumulator and a fast 18×18 multiplier.
Memory Controller Block
The systems also feature integrated Memory Controller blocks that allow data rates that can reach up to 800MB/s. Their multi-port framework comes with an independent FIFO that lowers designing timing issues. The systems can support LPDDR, DDR3, DDR2, and DDR. They also have block RAM that offers a range of granularity. Their CMT or Clock Management Tile is designed to improve performance. The simplified configuration of Spartan 6 FPGA systems allows for low-cost support while their enhanced security is designed for protection. They also feature leading reference and IP designs.